VM Live Migration Algorithm Optimization
Published:
In this project I came up with a idea for speedup up VM migration and wrote a simple simulator to study the behavior of different live migration algorithm.
Projects
gRPC acceleration with TAS
Published:
In this project we accelerate a popular RPC framework gRPC with TAS, an tcp compatible transport
FPGA TCP Packet Parser
Published:
Implement a TCP packet parser on Zynq FPGA, assemble and processing the message at FPGA NIC instead of going all the way to CPU
Parallel Traffic Simulator with Regent
Published:
In this project we accelerate the solution of Traffic Assignment Problem (TAP) which Regent.
VLSI Design Labs
Published:
Course Labs for EE382M-7 VLSI-1 taught at UT Austin in Fall 18
FPGA-based Fault Injection Platform
Published:
Fault injection platform based on Rocketchip generator
FPGA Page Rank Accelerator
Published:
Design and Implement a page-rank accelerator on Xilinx Zynq FPGA.
Computer Architecture Course Labs
Published:
Course Labs for EE382N Computer Archtecutre at UT Austin in Fall 17
SPICE Netlist Simulator Implementation
Published:
Design and Implement a SPICE netlist simulator in python.
GPU Acceleration for CNN on Mobile Platforms
Published:
Using GPU on mobile SoC for CNN inference acceleration